Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1(a) Explain the following canonical form :
i) F(x, y, z) = x + x y + x z
ii) F(x, y, z) = (x + z)(x + y)(y + z)
10 M
1(b) Find the minimal POS expression of incompletely specified Boolean function using k-map,
f(a, b, c, d) = πM(1, 2, 3, 4, 9, 10) + πd(0, 14, 15).
5 M
1(c) Find all the minimal SOP expression of
f(a, b, c, d) = ∑(6, 7, 9, 10, 13) + ∑d(1, 4, 5, 11, 15) using k-map.
5 M

2(a) Find all the prime implicants of the function :
f(a, b, c, d) = ∑(7, 9, 12, 13, 14, 15) + ∑d (4, 11) using Quine - MaClusky's algorithm.
10 M
2(b) For a given incomplete Boolean function, find a minimal sum and minimal product expression using MEV technique taking least significant bit as map entered variable.
f(a, b, c, d) = ∑(1, 5, 6, 7, 9, 11, 12, 13) + ∑d(0, 3, 4).
10 M

3(a) Implement the funtion using active low output dual 2 : 4 line decoder IC74139
i) f1(A, B, C) = ∑m (0, 1, 2, 5)
ii) f2(A, B, C) = πM (1, 3, 4, 7).
10 M
3(b) Design priority encoder with three inputs, with middle bit at highest priority encoding to 10, most significant bit at next priority encoding to 11 and least significant at least priority encoding 01.
10 M

4(a) Define multiplexer and demultiplexer and draw block diagram.
4 M
4(b) Design 4 : 1 multiplexer, draw the circuit using gates.
6 M
4(c) Explain how will you implement the following function using implementation table,
F(A, B, C, D)= ∑m(0, 1, 3, 4, 7, 10, 12, 14) with A, B, C as select lines.
10 M

5(a) Design full adder and draw the circuit using two input NAND gates.
7 M
5(b) Design and draw the circuit of look ahead carry generator using gates. Draw the block diagram of 4-bit parallel adder using look ahead carry generator.
10 M
5(c) Design single bit magnitude comparator and draw the circuit.
3 M

6(a) Obtain the following for SR flip-flop :
i) Characteristics equation
ii) Excitation table
iii) State diagram
6 M
6(b) With the help of a schematic diagram, explain how a serial shift register can be transformed into a i) ring counter ii) Johnson counter.
4 M
6(c) Design mod6 synchronous counter using D-flip-flops.
10 M

7(a) A sequential network has one input and one output the state diagram is shown in Fig. Q7(a). Design the sequential circuit using T flip-flops.
:!mage
10 M
7(b) Derive the transition equations, transition table, state table and state diagram for the following.
:!mage
10 M

Write notes on:
8(a) Mealy and Moore model
10 M
8(b) State machine notation.
10 M

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