MU Electronics Engineering (Semester 7)
Embedded System Design
December 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Answer the following questions.
1 (a) With the help of an example explain periodic task. List and explain the various types of tasks in an embedded system.
5 M
1 (b) With respect to power, performance and cost state and explain the associated design metrics for an embedded system.
5 M
1 (c) What are interrupts and explain the factors that contribute to interrupt response time in a system.
5 M
1 (d) Explain the structure of typical C source program for ARM based target processor. Typically list the various data types along-with memory size supported by a C compiler.
5 M

2 (a) What is a task and various states that a task can lie in for an embedded environment.
10 M
2 (b) Explain briefly the problem of priority inversion and mechanism to prevent the same.
10 M

3 (a) State and explain the criteria for tasks schedulability and explain various scheduling mechanisms.
10 M
3 (b) Explain briefly the register structure of Cortex-M3 architecture along with the function of various special registers.
10 M

4 (a) Distinguish between Cortex-M3 and M4 architecture and explain briefly the interrupt structure of M3 architecture.
8 M
4 (b) Explain the operation and significance of following MicroC/OS-II functions. (Any three). (i) OSInit(); (ii) OSSemPend(); & OSSemPost(); (iii) OSTaskCrete(); (iv) OSMboxPost(); & OSMboxPend();
12 M

5 (a) Write a brief note to bring out the comparison between Cortex - M3, A8 and R4 architectures.
10 M
5 (b) Explain the various inter-process/task communication tools like pipe, mailbox, message queue and semaphore used by an RTOS environment.
10 M

Write short notes on (Any two).
6 (a) Serial communication standard RS=232 and comparison with RS-485.
10 M
6 (b) Low power features in Cortex - M3 architecture.
10 M
6 (c) Black box and White box testing.
10 M



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