MU Elec Circuits & Comm. Fundamentals - May 2012 Exam Question Paper

MU Computer Engineering (Semester 3)
Elec Circuits & Comm. Fundamentals
May 2012

Total marks: --
Total time: --

INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1(a) Draw re model and h model of CE amplifier configuration

4 M

1(b) Investigate the effect of I_b on the performance of inverting amplifier, if I_b=10nA and all resistances are 100K ohm. What dummy resistance R_p must be installed in series with the non-inverting input to minimize E₀?

4 M

1(c) List features of IC 723 regulator

4 M

1(d) Explain two static and dynamic parameters of op-amp

4 M

1(e) Why voltage divider biasing is widely used?

4 M

2(a) Draw the circuit diagram of 3 op-amp instrumentation amplifier using IC741. Explain its requirements, applications and its disadvantages over difference amplifier.

12 M

2(b) Derive equations for Z_i, Z₀ and A_v for CE amplifier using voltage divider network (with un-bypassed R_e)

8 M

3(a) Why is an emitter coupled differential amplifier RE resistor is replaced by constant current source. Draw such circuit. Explain how this network acts as a constant current source (I₀)

10 M

3(b) For n-channel FET (un-bypassed Rs) with R1=910k ohm, R2=110k ohm , RD=2.2k ohm , RS= 510 ohm, IDSS=5.8mA , Vp=-3V and VGSS=-2V. Find ID, VGS, VG, VD, VS, and VDS (common source circuit)

10 M

4(a) Design a mono-stable multi-vibrator to generate a pulse of 1.1ms. Draw circuit diagram with trigger circuits waveforms obtained at pin 3 across capacitor.

10 M

4(b) Draw and explain working of R-2R ladder network and the following terms:
i. Resolution
ii. Offset voltage
iii. Full scale voltage

10 M

5(a) Draw and explain block diagram of IC 723 regulator and also explain need of short circuit protection circuitory

10 M

5(b) Draw neat functional diagram of PLL IC 555 and explain the following terms along with working of PLL:
i. Free running frequency
ii. Capture range
iii. Lock range

10 M

6(a) Explain Op-amp as summer and comparator

10 M

6(b) Compare ideal and practical integrator circuit

10 M

7(a) Schmitt trigger circuit

5 M

7(b) Successive approximation resistor analogue to digital convertor

5 M

7(c) FET characteristics

5 M

7(d) Wein bridge Oscillator

5 M

7(e) Stability factor of biasing circuit.

5 M

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