MU Electrical Engineering (Semester 7)
Control System - 2
December 2016
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


1(a) From Bode plot perspective, briefly explain how the lag network does not appreciably affect the speed of trasient response.
5 M
1(b) Describe the physical meaning of conrtrollability and explain how controllability of a matrix can be determined mathematically.
5 M
1(c) Describe how digital compensators can be designed from the s-plane.
5 M
1(d) How many words occupied by the counter instruction in the counter file? Explain the content of each word in detail.
5 M

2(a) Find the static error constant and the steady state error for the digital system with feed forward transfer function, \(G(z)=\frac{0.13(z+1)}{(z-1)^2(z-0.74)} \)/ with sampling time T=0.1, if the input is 2u(t)+5tu+8t2u(t). What modification to be done to drive the steady state error of this system to zero?
10 M
2(b) Explain the relationship between the number assigned to the data files in memory and the number used by the input and output modules in PLC with example and diagrams.
10 M

3(a) Consider a unity feedback system with feed forward transfer function \( G(s)=\frac{K}{s(s+5)(s+20)}\)/. The uncompensated system has Kv=10,
%OS=55% and TP=0.5seconds. Use lead compensator to reduce the percent overshoot to 10% while keeping the peak time and steady state error about the same or less.
10 M
3(b) Prove that the transform of the sampled output is the product of the transform of the sampled input and pulse tranfer function of the system and thus derive pulse transfer function of the system.
10 M

4(a) Explain the program files and data files in PLC.
10 M
4(b) Explain the scan cycle of PLC.
5 M
4(c) Explain Jump and Label operation in PLC with example.
5 M

5(a) Design and observer for the plant \(G(s)=\frac{50}{(s+3)(s+6)(s+9)} \)/ represented in phase variable from with a desired performance of 10% overshoot and a settling time 0.5 second. The observer will be 10 times faster than the plant. Design the observer by first converting to observer canonical form. Draw the phase variable representation with the observer gains.
15 M
5(b) Explain how to design systems represented in state space for zero steady state error with help of block diagram and state equations.
5 M

6(a) What is the cause of integral wind up in PI conroller? How this will affect the performance of the system? Explain how it can be removed with block diagrams and wave forms.
10 M
6(b) Explain reverse acting controller.
5 M
6(c) Represent the following plant \( G(s)=\frac{(s+4)}{(s-1)(s+2)(s+5)} \)/ in controller canonical from and design the state variable feedback controller to yield a 20.8% overshoot and settling time of 4 seconds.
5 M



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