RGPV Electronics and Communication Engineering (Semester 3)
Computer System Organization
December 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


1(a) What is memory reference instruction?
2 M
1(b) Write the differences between addres bus and the data bus.
2 M
1(c) Draw Von-Neumann architecture. What is meant by Von-Neumann bottleneck?
3 M
Solve any one question from Q.1(d) & Q.1(e)
1(d) What is instruction cycle? Explain different phases of instruction cycle and show flow chart for instruction cycle.
7 M
1(e) What is register? Explain various types of register.
7 M

2(a) Draw flow chart for decimal multiplication.
2 M
2(b) What is Hardwired control unit?
2 M
2(c) Write a brief notes on shift micro operation.
3 M
Solve any one question from Q.2(d) & Q.2(e)
2(d) With neat block diagram, explain working principal of micro program sequencer.
7 M
2(e) Draw flow chart to explain how addition and subtraction of two fixed point number can be done.
7 M

3(a) What is Priority interrupt?
2 M
3(b) List the features of IOP.
2 M
3(c) Write the difference between programmed I/O and interrupt-driven I/O.
3 M
Solve any one question from Q.3(d) & Q.3(e)
3(d) Draw the block diagram of DMA transfer in computer system and explain.
7 M
3(e) Explain in brief programmed I/O and interrupt initiated I/O.
7 M

4(a) What is memory hierarchy?
2 M
4(b) What is Content Addressable Memory? What are its advantages?
2 M
4(c) Explain hit ratio in cache organization.
3 M
Solve any one question from Q.4(d) & Q.4(e)
4(d) Give short notes on Virtual memory organization.
7 M
4(e) Define the following terms:-
Write through cache ii) Direct mapping
7 M

5(a) What is Flynn's Taxonomy?
2 M
5(b) Write the characteristics of multiprocessor.
2 M
5(c) Differentiate between loosely coupled and closely coupled multiprocessor configuration.
3 M
Solve any one question from Q.5(d) & Q.5(e)
5(d) Write the various performance issues in pipelining.
7 M
5(e) What are Interconnection structure? Explain the scheme crossbar switch in detail.
7 M



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