MU Computer Engineering (Semester 4)
Computer Organization and Architecture
May 2016
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Attempt any 4 sub questions.
1(a) Explain various pipeline hazards.
5 M
1(b) Express (35.25)10 in the IEEE single precision standard of floating point representation.
5 M
1(c) Explain in brief the function of 8089 I/O processor.
5 M
1(d) Compare RISC and CISC processors.
5 M
1(e) Differentiate between Computer Architecture and Computer organization.
5 M

2(a) Explain Flynn's classification in detail.
10 M
2(b) Explain the Interleaved memory.
10 M

3(a) Calculate number of page faults and page hits for the page replacement policies FIFO. Optimal & LRU for given reference string 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 1, 2, 0, 1, 7, 0, 1 (assuming three frame size).
10 M
3(b) What is the need of DMA? Explain its various techniques of data transfer.
10 M

4(a) What is Bus arbitration? Explain its techniques.
10 M
4(b) Describe the register organization within the CPU.
10 M

5(a) What are the features of cache memory design?
10 M
5(b) Multiply (-10) and (-4) using Booth's algorithm.
10 M

Write notes on
6(a) Joysticks
6 M
6(b) The characteristics of memory
8 M
6(c) Microinstructions to execute an instruction MOV [R1], R2.
6 M



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