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VTU Electrical and Electronic Engineering (Semester 3)
Analog Electronic Circuits
May 2016
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1(a) Explain Reverse recovery time of a semiconductor diode.
6 M
1(a) Explain the following canonical form :
i) F(x, y, z) = x + x y + x z
ii) F(x, y, z) = (x + z)(x + y)(y + z)
10 M
1(b) The Fig. Q1 (b) shows two way clipper. Determine its output wave form. Assume diode drop of 0.7V.
:!mage
7 M
1(b) Find the minimal POS expression of incompletely specified Boolean function using k-map,
f(a, b, c, d) = πM(1, 2, 3, 4, 9, 10) + πd(0, 14, 15).
5 M
1(c) What is clamper circuit? Explain the operation of Positive and Negative clamper circuit and draw the wave form. [Assume Ideal Diode].
7 M
1(c) Find all the minimal SOP expression of
f(a, b, c, d) = ∑(6, 7, 9, 10, 13) + ∑d(1, 4, 5, 11, 15) using k-map.
5 M

2(a) What is transistor? Discuss the causes of bias instability in a transistor.
6 M
2(a) Find all the prime implicants of the function :
f(a, b, c, d) = ∑(7, 9, 12, 13, 14, 15) + ∑d (4, 11) using Quine - MaClusky's algorithm.
10 M
2(b) Derive the expression for IB, VCE and S(ICO) for voltage divider bias using exact analysis.
7 M
2(b) For a given incomplete Boolean function, find a minimal sum and minimal product expression using MEV technique taking least significant bit as map entered variable.
f(a, b, c, d) = ∑(1, 5, 6, 7, 9, 11, 12, 13) + ∑d(0, 3, 4).
10 M
2(c) For the circuit shown in Fig. Q2. Find IB, IC, VCE, VC and VE. Assume β = 100. VBE = 0.7.
:!mage
7 M

3(a) For common base configration shown in Fig. Q3(a). Find re, zi, z0 and Av.
:!mage
6 M
3(a) Implement the funtion using active low output dual 2 : 4 line decoder IC74139
i) f1(A, B, C) = ∑m (0, 1, 2, 5)
ii) f2(A, B, C) = πM (1, 3, 4, 7).
10 M
3(b) Derive an expresion for zi, z0, Av and Ai of a CE fixed bias configuration using re model.
7 M
3(b) Design priority encoder with three inputs, with middle bit at highest priority encoding to 10, most significant bit at next priority encoding to 11 and least significant at least priority encoding 01.
10 M
3(c) Using h-parameter model for a transistor in C.E. configuration. Derive expression for AI, zi and Av.
7 M

4(a) An amplifier consists of 3 identical stages in cascade; the bandwidth of overall amplifier extends from 20Hz to 20KHz. Calculate the band width of individual stage.
6 M
4(a) Define multiplexer and demultiplexer and draw block diagram.
4 M
4(b) Describe miller effect and derive an equation for miller input and output capacitance.
7 M
4(b) Design 4 : 1 multiplexer, draw the circuit using gates.
6 M
4(c) Draw and explain frequency response of an amplifier and briefly discuss the effect of various capacitors on frequency response.
7 M
4(c) Explain how will you implement the following function using implementation table,
F(A, B, C, D)= ∑m(0, 1, 3, 4, 7, 10, 12, 14) with A, B, C as select lines.
10 M

5(a) Explain the need of cascade amplifier and list the advantage of this circuit.
6 M
5(a) Design full adder and draw the circuit using two input NAND gates.
7 M
5(b) With block diagram, explain the concept of feedback. List the advantages of negative feedback.
7 M
5(b) Design and draw the circuit of look ahead carry generator using gates. Draw the block diagram of 4-bit parallel adder using look ahead carry generator.
10 M
5(c) Derive the expression for input resistance (Rif) for voltage series feedback amplifier.
7 M
5(c) Design single bit magnitude comparator and draw the circuit.
3 M

6(a) Draw input and output wave forms of class - A, Class - B and Class - C power amplifiers based on the location of Q - point, and briefly discuss.
6 M
6(a) Obtain the following for SR flip-flop :
i) Characteristics equation
ii) Excitation table
iii) State diagram
6 M
6(b) Draw the circuit diagram of series fed directly coupled Class - A amplifier. Give the expression for dc power input and a.c power output and show that efficiency is 25%.
7 M
6(b) With the help of a schematic diagram, explain how a serial shift register can be transformed into a i) ring counter ii) Johnson counter.
4 M
6(c) What is Harmonic distortion? Calculate the harmonic distortion components for an output signal having fundamental amplitude of 2.5V second harmonic amplitude of 0.25V, third harmonic amplitude of 0.1V and fourth harmonic amplitude of 0.05V. Also calculate the total harmonic distortion.
7 M
6(c) Design mod6 synchronous counter using D-flip-flops.
10 M

7(a) With neat circuit diagram explain the operation of BJT Hartley oscillator.
6 M
7(a) A sequential network has one input and one output the state diagram is shown in Fig. Q7(a). Design the sequential circuit using T flip-flops.
:!mage
10 M
7(b) i) The frequency sensitive arms of the bridge oscillator uses C1 = C2 = 0.001μF and R1 = 10KΩ while R2 is kept variable. The frequency is to be varied from 10KHz to 50KHz by varying R2. Find the minimum and maximum values of R2.
ii) Design the value of an inductor to be used in Colpitts oscillator to generate a frequency of 10MHz. The circuit is used a value of C1 = 100pF and C2 = 50pF.
7 M
7(b) Derive the transition equations, transition table, state table and state diagram for the following.
:!mage
10 M
7(c) With neat circui explain the working of series resonant crystal oscillator. A crystal has L = 0.1H, C = 0.01pF find the series resonating frequency.
7 M

8(a) Define transconductance gm and derive expression for gm.
6 M
Write notes on:
8(a) Mealy and Moore model
10 M
8(b) With equivalent model of JFET common drain configuration. Obtain the expression for zi, z0, Av.
7 M
8(b) State machine notation.
10 M
8(c) For common gate amplifier as shown in Fig Q8(c), gm = 2.8ms, rd = 50kΩ Calculate zi, z0, Av.
:!mage
7 M

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